The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Conventional IC processing involves forming one or more contacts to various features of an IC. For example, oftentimes, contact openings are simultaneously formed to areas of a substrate (or wafer) (e.g., doped regions) and gate structures disposed thereover. It has been observed that the traditional processes for forming contact openings to the substrate and gate structures may result in etching portions of the gate structure, such as the gate stack (e.g., a polysilicon and/or gate electrode). This over-etching of the gate structure can lead to undesirable contact resistance and degrade device performance.
Accordingly, what is needed is a method for manufacturing an integrated circuit device that addresses the above stated issues.